As field effect transistors (“FET”), such as PFETs and NFETs, are scaled down in size, semiconductor manufactures have utilized gate dielectrics having a high dielectric constant (“high-k”) to improve FET performance and reliability. High-k gate dielectrics are desirable in small feature size technologies since conventional gate dielectrics, such as silicon dioxide (“SiO2”), are too thin and they result in high tunneling current, as well as other problems, which decrease performance and reliability of FETs. However, when a high-k gate dielectric layer is formed on a silicon substrate in a conventional FET fabrication process, an unintentional layer of low quality silicon dioxide forms at the interface between the silicon substrate and the high-k gate dielectric layer, which can degrade the performance of the FET.
In a conventional process for fabricating a FET having a high-k gate dielectric, a high-k dielectric layer comprising, for example, hafnium oxide or zirconium oxide, is generally formed over a channel region of a substrate at a relatively low temperature. As a result, oxygen in the high-k dielectric layer can diffuse out of the high-k dielectric layer and combine with silicon in the substrate to form an interfacial layer of thermally grown SiO2 at the high-k dielectric/substrate interface. The interfacial layer formed in the above manner comprises an undesirable non-uniform, low quality SiO2, which has pin-hole defects as a result of the relatively low temperature at which the SiO2 is typically grown. Furthermore, since interfacial layer has a low dielectric constant and a typical thickness of approximately 10.0 Angstroms, the interfacial layer causes an undesirable reduction in the effective dielectric constant value between a gate electrode formed over the high-k dielectric layer and the substrate. Consequently, as a result of low quality, non-uniformity, pin-hole defects, and the relative thickness of the thermally grown SiO2 in the interfacial layer, the performance of the FET can be undesirably degraded.
Thus, there is a need in the art for an effective method for forming a field effect transistor having a high-k dielectric without forming a low-quality thermal silicon dioxide at the high-k dielectric/substrate interface.